Register; Logout; Contact us; Board index English Forum Explore General Discussion; Interrupt low Latency - again. To solve this problem, you must activate the desired effect and this is done with the following command. The ESP32 is communicating with a PIC16 microcontroller through an I2C bus. When the Wifi is working the edge detection and the callback function execution is delayed. All transactions must be handled by the CPU, which means that the transfers and responses are not real-time, and there might be noticeable latency. With Wifi *disabled*, I get a control loop latency of ~6ms . Because there are more interrupt sources than interrupts, sometimes it makes sense to share an interrupt in multiple drivers. 15 postsWriting into a queue in order to handle the interrupt in another task takes way too much time (about 13 us). RTOS task notifications can only be used when there is only one task that can be the recipient of the event. Post by ESP_igrr » Mon Nov 07, 2016 11:36 am . Delta_G January 28, 2016, 1:40am 4. and at T=9. Through oscillometer I found the interval between the pulse and spi cs signal was as much as 100~200 us, while this thread says the interrupt latency can be reduced to about 2 us. 25VDD and the minimum voltage for the high input os 0. ESP_igrr Posts: 1969 Joined: Tue Dec 01, 2015 8:37 am. As far as I know, ESP32 has no Schmitt trigger inputs, so what you get is the expected behaviour. The PLIC adds another 3 cycles from an external interrupt source. Creating and starting a timer, and dispatching the callback takes some time. Jose Silva Posts: 1 Joined: Fri Mar 18, 2022 4:19 am. One is to use the semaphore (s. IRQ Startup latency. The ESP32-S2 has one core, with 32 interrupts. The wording they used in "ESP32 Technical Reference manual", Chapter 5. A event handler is registered and can be called correctly, but the. An Operating system (OS) is nothing but a collection of system calls or functions which provides an interface between hardware and application programs. tool-cmake. Each CPU has its own interrupt latency which is dictated by the. INTENABLE & INTERRUPT gives the bitmask set of currently asserted and enabled interrupts. Interrupt latency on the ESP32 is in the order of microseconds, unfortunately; there's a fair amount of prologue going on. I want to make a counter that can count the time between pulses in nanoseconds. 5 posts • Page 1 of 1. 3. sdk: IDF V4. bmakovecki Posts: 4 Joined: Fri Nov 03, 2017 9:20 pm. We can enable interrupt on any of these GPIO pins by. In the interrupt handler itself I only set a variable that causes the execution of a function in the loop. It would be good to find a way to have interrupt handlers on the ESP32 have consistent and low latency. Calling a C function from an interrupt requires the CPU's context to be saved, and the call stack to be switch to that of the C ISR. At its heart, there's a dual-core or single-core. Post by tankist » Thu Feb 10, 2022 7:08 am . Re: External Interrupt Latency. This is useful for interrupts which need a guaranteed minimum execution latency, as flash write and erase operations can be slow (erases can take tens or hundreds of. There are several factors that affect the interrupt latency including the microcontroller’s architecture/design, clock speed, type of interrupt controller used. Post by mTron47 » Fri Jul 13, 2018 3:39 pm . They are all 64-bit (54-bit for ESP32-C3) generic timers based on 16-bit pre-scalers and 64-bit (54-bit for ESP32-C3) up / down counters which are capable of being auto-reloaded. esp32 GPIO interrupt latency. At 17uS, the esp32 responds to the event and sets an IO line to respond, which is too late. 4 GHz Wi-Fi (802. Post by bmakovecki ». Post by jfmateos » Mon Nov 07, 2016 9:03 am . 35uS, the master brings the line high. Therefore, there is a lower limit to the timeout value of one-shot esp_timer. The Xtensa architecture supports 32 interrupts, divided over 7 priority levels from level 1 to 7, with level 7 being an non-maskable interrupt (NMI), plus an assortment of exceptions. 04 in a VirtualBox. Register; Logout; Contact us; Board index English Forum Explore General Discussion; Interrupt low Latency - again. Transmitter code. tankist Posts: 5 Joined: Tue Feb 08, 2022 7:22 am. ) This means interrupt latency is about 2uS, which means that at 1MHz, the first interrupt isn't finished yet. Andreas’s test method uses the ESP32 SDK via Arduino IDE. GPIO Interrupt Latency - once more. Typically, if using the Arduino AttachInterrupt thingy in setup () the interrupt will be attached to core1. The problem is that I want to reduce the current latency time I have (2 ms). esp_timer set of APIs provides one-shot and periodic timers, microsecond time resolution, and 64-bit range. Using either the first or both pins with interrupts works very well. Interrupt Latency Requirements Encoder requires low latency response to changes of the signals. First of all, the timer should be initialized by calling the function timer_init() and passing a structure. ESP_Sprite Posts: 8410 Joined: Thu Nov 26, 2015 4:08 am. Setting a bit and polling this bit in another task within an infinite loop is faster (2 us), but cannot be a real option, because this is waste of resources and prevents from deep sleep options. for (;;) { } } gcjr:Reading the registers/state of another core. I think there has been a little bit of progress, although not specifically for this purpose: the GPIO drivers have been optimized a bit so if you use the ESP-IDF API, your interrupt latency should be a bit lower (but not as low as using the bare metal), and ESP-IDF now allows you to have high-prio assembly. The operating system switches task base on priority. ISR – is the name of the function that. Each interrupt has a programmable priority level. The interrupt source is a GPIO that connects to pulse-per-second signal from a GPS module. A event handler is registered and can be called correctly, but the. The counter starts to count when a pulse enters a pin (at the start of the pulse) then stops when a second pulse comes. In the core0 task I set up a timer interrupt that signals to the task (through the interruptCounter variable) to toggle a pin every 100 us. I'm detecting another delay related with the GPIO interrupts from ESP32. It also takes 26uS to process the IRQ body, though I am using QueueSendfromISR in the. It also takes 26uS to process the IRQ body, though I am using QueueSendfromISR in the. Interrupt low Latency - again. None of them is induced by the abort in your modified esp_timer_impl_set_alarm code. When the voltage on the input is beetween those values, you can expect undefined behaviour. Setting a bit and polling this bit in another task within an infinite loop is faster (2 us), but cannot be a real option, because this is waste of resources and prevents from deep sleep options. An interrupt service routine should be as light as possible so that it can service an interrupt quickly. Minimum extra latency is 0. ESP32 Interrupt Latency Measurement Interrupt Latency – is the time it takes the CPU to respond to a specific interrupt signal. Hi, I am having trouble with the external interrupt latency being very inconsistent. I seem to remember recent ESP-IDF versions have some allowances to also run C high-level interrupts, but I don't have the details on that. Espressif ESP32 Official Forum. But the difference is speed as stated earlier. Not the stm IDEs. Core 0 is known as the “Protocol Core” or “PRO CPU. It also takes 26uS to process the IRQ body, though I am using QueueSendfromISR in the. IRQ Startup latency. Apparently the expected interrupt latency is around 2 us; alternatively you can write your own high level interrupt handlers in assembler. Now I have found the time to do it for myself and with the ESP32 and some other platforms. bmakovecki Posts: 4 Joined: Fri Nov 03, 2017 9:20 pm. Minimum extra latency is 0. I am seeing a similar issue as noted here:. Lately, I've been working on a project that consists of programming a Z80 with 8 address and data lines, the clock is done with ledc, it has two external interrupts on the Z80's WR and RD pins --> ESP32. Re: Interrupt low Latency - again. Sensor Shell Module Sample. Hi, I am having trouble with the external interrupt latency being very inconsistent. 2 posts • Page 1 of 1. An esp32 can do the job but is overkill and will be adding a complexity you do not need when learning C. Espressif ESP32 Official Forum. I'm setting another GPIO pin to high when entering the event handler, and. Register; Logout; Contact us; Board index English Forum Explore General Discussion; Interrupt low Latency - again. h> // Include Serial Peripheral. The ESP32 has two cores, with 32 interrupts each. Refer to “ESP32 practical power saving” for a detailed description on sleep mode. Generic Proximity Sensor Sample. There are no native software interrupts in Arduino UNO (Atmega328p) microcontroller. This method is useful for some simple callbacks which aim for lower latency. I think there has been a little bit of progress, although not specifically for this purpose: the GPIO drivers have been optimized a bit so if you use the ESP-IDF API, your interrupt latency should be a bit lower (but not as low as using the bare metal), and ESP-IDF now allows you to have high-prio assembly interrupt handlers without having to copy-paste the ESP-IDF vector/startup code integrally. Each interrupt has a programmable priority level. If there was a very small interrupt <10 cycles, it probably wouldn't notice and would keep going, however, if I do 12 MBit USB, then, there is no timer, I'll simply be relying on the time it takes to execute every. To make the static function work, it can only access static variables. Therefore, there is a lower limit to the timeout value of one-shot esp_timer. We even have the NMI free, in theory, that should 100% guarantee you interrupt latency. Re: External Interrupt Latency. SPI Latency. 115200 baud is possible. Only in the case where an RTOS task notification is used in place of a. The esp_intr_alloc abstraction exists to hide all these. Post by edigi32 » Tue Feb 26, 2019 9:57 am . This is double the 40 MHz default value and doubles the speed at which code is loaded or executed from flash. esp32 GPIO interrupt latency. Application Controlled Deferred Interrupt Handling Application controlled deferred interrupt handling is so called because each interrupt that uses this method executes in the context of a task created by the application writer. Let it be A8 pin for example! ( The LED Pin) Step4: Click On The Pin You Want To Configure As An External Interrupt Input. GPIO Interrupt Latency - once more. esp32 GPIO interrupt latency. At first, I thought the I2C was hanging in the ESP32 but I can see that the problem. The third argument is the mode. Top. jeromeh Posts: 31 Joined: Thu Dec 22, 2016 5:41 am. Interrupt latency on the ESP32 is in the order of microseconds, unfortunately; there's a fair amount of prologue going on. Setting a bit and polling this bit in another task within an infinite loop is faster (2 us), but cannot be a real option, because this is waste of resources and prevents from deep sleep options. Espressif ESP32 Official Forum. Interrupt low Latency - again. the AC module is powered by the 3V3 regulator of the ESP32 dev board. 6. The MIPS chip I'd like to replace currently does it in 225 ns at 80 MHz (18 clock cycles), and any increase is likely to make things no longer work. This is double the 40 MHz default value and doubles the speed at which code is loaded or executed from flash. Use this function if an RTC IO needs to be disconnected from internal circuits in deep sleep, to minimize leakage current. Reading the registers/state of another core. , for low latency operations), set the ESP_INTR_FLAG_IRAM flag when the interrupt handler is registered. Here you could see that the interrupt latency is almost 1usec and the ISR execution time is 2. Example Software. Ive measured the response by sending the same data I recieve through the TX output of the UART. 1 Xtensa® Dual-Core 32bit LX7 Microprocessor The microprocessor for the ESP32-S3 SoC inside the NORA-W106 module is a dual-core 32. 2 us (when the CPU frequency is 240 MHz and frequency scaling is not enabled). Timer callbacks are dispatched directly from the timer interrupt handler. . 35uS, the master brings the line high. This is useful for interrupts which need a guaranteed minimum execution latency, as flash write and erase operations can be slow (erases can take tens or hundreds of milliseconds to. On the ESP32, the Interrupt Allocation can route most interrupt sources to these interrupts via the interrupt mux. Now I have found the time to do it for myself and with the ESP32 and some other platforms. External Interrupt Latency. But when the interrupt latency is longer than the narrowest pulse from ledc the edge polarity detection fails and the output-pair is wrong. println (xPortGetCoreID ()); You should see "Current CPU core 1" as output (the cores are normally numbered 0 and 1). esp32 GPIO interrupt latency. ESP32 GPIO Interrupts. On high level interrupt (GPIO_NUM_35) we are having an ADC (Analog to digital converter) which gives us an. When an interrupt is triggered, the processor halts the execution of the main program. Methods. When PCIE0 (bit 0) is set, then the. This getting started user guide focuses on ESP-MESH networking protocol by Espressif. Now I have found the time to do it for myself and with the ESP32 and some other platforms. The two ESP32 timer groups, with two timer(s) in each, provide the total of four individual timers for use. So we can make switchChanged static. SHT3XD: High accuracy digital I2C humidity sensor. Now I have found the time to do it for myself and with the ESP32 and some other platforms. Setting a bit and polling this bit in another task within an infinite loop is faster (2 us), but cannot be a real option, because this is waste of resources and prevents from deep sleep options. In the first behavior, the latency is around 3 us, but sometimes there is a variation (jitter) and the rise of the output signal takes 15 us or even more to keep up with the input. 1. I am seeing a similar issue as noted here:. The tests were performed on a DFRobot’s ESP-WROOM-32 device integrated in a ESP32 FireBeetle board. ESP32-C3 features four predefined power modes that not only enable developers to fulfill the requirements of various IoT application scenar- ios but also pass rigorous power consumption. For ESP32-S3, this value can be set to 80 MHz, 160 MHz, or 240 MHz. Board index English Forum Discussion Forum ESP-IDF; Reduce external interrupt latency. Board index English Forum Discussion Forum ESP-IDF; Reduce external interrupt latencyWriting into a queue in order to handle the interrupt in another task takes way too much time (about 13 us). Top. jeromeh Posts: 31 Joined: Thu Dec 22, 2016 5:41 am. Now I believe timer interrupt will be a better option as we will not need the task to be running all the time. 04 in a VirtualBox. It is possible to implement non IRAM-Safe Interrupt and place ISR handler into flash memory but it might be interrupt latency when flash access functions are used (disable CPU. esp32 GPIO interrupt latency. GPIO Summary. A GPIO interrupt is a form of an external interrupt where an external trigger signal occurs when a key is pressed down (for example). The Nano ESP32 features the NORA-W106-10B stand alone radio module, embedding an ESP32-S3 series SoC as well as an embedded antenna. h file allows an application to use a read only timer for timing measurements done at and below 1 microsecond level. The purpose of the IWDT is to ensure that interrupt service routines (ISRs) are not blocked from running for a prolonged period of time (i. If using interrupts with multiple modules, since they are open drain they can be tied together if a single interrupt back to the MCU is desired. Hi, I'm using a GPIO pin as a external interrupt, responding to negedge events. In case of IRAM-safe interrupt you should use the HAL functions to read/write data from UART FIFO or directly read/write data to peripheral registers. I would like to know the interrupt latency for an external pin interrupt in ESP32. The ESP32-C6 combines 2. Interrupt routine is done in assembler (and working stable). Top. I would like to know the interrupt latency for an external pin interrupt in ESP32. Espressif ESP32 Official Forum. For some reason, the traceback for case C could not be decoded by EspExceptionDecoder. 04 in a VirtualBox. Post by ESP_igrr » Mon Nov 07, 2016 11:36 am . The ESP32-S2 chip features 43 physical GPIO pins (GPIO0 ~ GPIO21 and GPIO26 ~ GPIO46). MPU6050: Invensense Motion Tracking Device. It’s a measure for the response time of an interrupt and it’s desired to be as small as. Post by go4retro » Thu Jan 10, 2019 6:26 am . Espressif ESP32 High Resolution Timer. I can not figure out how to remove buffer or increase size to as close as possible real time transmission. Post by MiguelMagno » Mon Aug 21, 2023 10:31 pm . Each interrupt has a certain priority level, most (but not all) interrupts are connected to the interrupt mux. Return. Setting a bit and polling this bit in another task within an infinite loop is faster (2 us), but cannot be a real option, because this is waste of resources and prevents from deep sleep options. Re: Comment about low-latency interrupts #52669. Well that sounds like a shortcoming. 4 GHz Wi-Fi and Bluetooth 5 (LE) with a long-range support. That needs 2 µs latency to start the waiting task RTOS_2 in core 0. Top. Because there are more interrupt sources than interrupts, sometimes it makes sense to share an interrupt in multiple drivers. But anyway, we know for sure that the dedicated external interrupt pins. Because there are more interrupt sources than. Improving Overall Speed. Through oscillometer I found the interval between the pulse and spi cs signal was as much as 100~200 us, while this thread says the interrupt latency can be reduced to about 2 us. 04 in a VirtualBox. Espressif ESP32 Official Forum. Interrupts sensitive to pin logical level take into account GPIO_ACTIVE_LOW flag. Espressif ESP32 Official Forum. The kernel addresses such use-cases by allowing interrupts with critical latency constraints to execute at a priority level that cannot be blocked by interrupt locking. CMake is an open-source, cross-platform family of tools designed to build, test and package software. The ESP32-S3 has two cores, with 32 interrupts each. In this last example project, we’ll test multiple Arduino Timer Interrupts. One way to get around this is to write a high-level interrupt in assembly, but that is non-trivial and I don't know if the Arduino environment supports it. In ESP-NOW, application data is encapsulated in a vendor-specific action frame and then transmitted from one Wi-Fi device to another without connection. mertkslkc May 30, 2021, 6:57pm 11. You can’t measure it, because the next operation might take a little longer! You don’t mention a. This assumes that the interrupt handler is in cache or ITIM. This time between the hardware IRQ and starting the execution of the ISR is called the Interrupt Latency and it’s demonstrated in more detail in the tutorial linked below. To use FreeRTOS timers, you have to turn them on with the following entry in FreeRTOSConfig. This method is useful for some simple callbacks which aim for lower latency. Using the SDK indeed does restrict the interrupt bandwidth to around 200khz. ESP32 external interrupt latency. cases. The Nano ESP32 features the ESP32-S3 system on a chip (SoC) from Espressif, which is embedded in the NORA-W106 module. Espressif ESP32 Official Forum. Re: handling GPIO interrupts. Post by mTron47 » Fri Jul 13, 2018 3:39 pm . Overview The ESP32-C3 has one core, with 31 interrupts. esp32 GPIO interrupt latency. :49 am. 2 posts. ESP_igrr Posts: 2066 Joined: Tue Dec 01, 2015 8:37 am. Espressif ESP32 Official Forum. Post by bmakovecki ». Interrupt latency on the ESP32 is a little higher than ESP8266, although there are also a lot of other variables which can effect interrupt timing. This adds some latency to the interrupt which, if excessive, can lead to the interrupt missing its deadline. If you can live with 2µs latency, move reaction code into the interrupt (got ~2µs this way, not always feasible, BTW). The next 1, 2 or 3. No, the problem is in that: With 1. I would like to know the interrupt latency for an external pin interrupt in ESP32. esp32 GPIO interrupt latency. I am a retired electrical engineer who has spent the last 15 years of his career in software engineering for other people. wdt. Hi, I'm using a GPIO pin as a external interrupt, responding to negedge events. Would it be possible to start a hardware timer in the first interrupt handler and then see how many ticks have elapsed in the second one? That feels as if it should give less latency and better resolution. Improving Overall Speed ¶. h: 1. The timer_u32. Timer callbacks are dispatched directly from the timer interrupt handler. we are doing some stuff with an external RF transceiver and need to respond to its interrupts as fast as (technically) possible. Without seeing and debugging the full code it's hard to tell what the problem might be. At 17uS, the esp32 responds to the event and sets an IO line to respond, which is too late. Depending on the project at hand I switch between two development environments: either ESP-IDF, running under Eclipse on Ubuntu 18. On a timer interrupt I write to all the DAC channels with successive spi_device_polling_transmits. Now I have found the time to do it for myself and with the ESP32 and some other platforms. The only way you are going to get microsecond stable interrupt latency is to code for bare metal and roll your own operating system. IRQ Startup latency. Example: Turn on an LED when a push button is pressed. 04 in a VirtualBox. Post by mTron47 » Fri Jul 13, 2018 3:39 pm . Writing into a queue in order to handle the interrupt in another task takes way too much time (about 13 us). Then you could replace it with your own and call the "original" wmac handler. That's how power-supply short circuits are avoided. There isn't any other device on the bus so when the PIC16 has new data available it generates a 50us low pulse on the SCL line, the ESP32 detects this pulse and starts reading data. greetings sdk: IDF V4. and at T=9. Install Drivers - Allocating ESP32’s resources for the UART driver. Step1: Open CubeMX & Create New Project. Setting a bit and polling this bit in another task within an infinite loop is faster (2 us), but cannot be a real option, because this is waste of resources and prevents from deep sleep options. Espressif Homepage;. However, the IRQ pins (INTx and PCINT) pins can be used in output mode. 9usec. 5 posts • Page 1 of 1. Interrupt low Latency - again. Re: External Interrupt Latency. Timer callbacks are dispatched directly from the timer interrupt handler. Writing into a queue in order to handle the interrupt in another task takes way too much time (about 13 us). But this is only applicable if you are using some of the RF features such as Wi-Fi or BLE. After that you get a cylcetime of ~300ns (disable interrupts for core 0). Espressif ESP32 Official Forum. ESP32 GPIO Interrupts. ESP32 interrupt latency is long and irregular #3894. The ESP32 has two cores, with 32 interrupts each. How can I minimize latency and execution time for interrupt ? I register interrupt as: Code: Select all. Post by bmakovecki ». I think there has been a little bit of progress, although not specifically for this purpose: the GPIO drivers have been optimized a bit so if you use the ESP-IDF API, your interrupt latency should be a bit lower (but not as low as using the bare metal), and ESP-IDF now allows you to have high-prio assembly. I think there has been a little bit of progress, although not specifically for this purpose: the GPIO drivers have been optimized a bit so if you use the ESP-IDF API, your interrupt latency should be a bit lower (but not as low as using the bare metal), and ESP-IDF now allows you to have high-prio assembly. 4, hd:ESP32-S3 when a pulse is detected by one io, an spi transaction will be triggered. 04 in a VirtualBox. Software interrupts are internal which occur in response to the execution of a software instruction. class myClass { static volatile bool switchChanged; // declare public: void begin () { pinMode (2, INPUT. and at T=9. I am seeing a similar issue as noted here:. Home; Quick links. These ESP boards are. jeromeh Posts: 31 Joined: Thu Dec 22, 2016 5:41 am. Now, if we use a timer, we can use a callback function to get triggered every interval. Alternatively, it may be enough to run the gpio_install_isr_service call on a task that is pinned to CPU1. Home; Quick links. (Accessing DRAM or other internal memory is fine; your data doesn't have to be in IRAM, just in internal RAM. BTW, for the goal you're aiming for (measuring pulse durations), timers in GPIO ISRs are not the best solution on the ESP32 (mostly due to interrupt latency : the ESP32 CPU is a lot more complex than simple 8-bit micros). External Interrupt Latency. I think there has been a little bit of progress, although not specifically for this purpose: the GPIO drivers have been optimized a bit so if you use the ESP-IDF API, your interrupt latency should be a bit lower (but not as low as using the bare metal), and ESP-IDF now allows you to have high-prio assembly. The esp_intr_alloc () abstraction exists to hide all these. Resolution timer_u32 uses 80 MHz clock (in most. Because there are more interrupt sources than interrupts, sometimes it makes sense to share an interrupt in multiple drivers. Home; Quick links. This process is generally time consuming (currently clocks in at approximately a few microseconds on the ESP32) and is not suited for High Level interrupts since they're meant. Through oscillometer I found the interval between the pulse and spi cs signal was as much as 100~200 us, while this thread says the interrupt latency can be reduced to about 2 us. STM32 ESP32 ARDUINO PIC Electronics. This comes at the expense of long interrupt latency (~ 1ms). Don't expect any miracles (and especially not 10-20ns); because of the Xtensa architecture, handling interrupts in C is pretty costly. How to put in light sleep ESP32. As most of the base stuff runs on CPU0, CPU1 has fewer things to mess with the latency. bmakovecki Posts: 4 Joined: Fri Nov 03, 2017 9:20 pm. CTR with CBC-MAC Protocol (CCMP) is used to protect the action frame for security. STM32 Interrupt Latency. The loop works as follows: The ADC notifies the ESP32-S3 through an ALERT pin interrupt, the ISR sets a ready flag. The main issue here is the way the interrupt handler work by storing a table of the ISR function pointer for each core. The code is functional, but I can't work with. Overview. I'm trying to implement a high level interrupt to reduce the interrupt latency and jitter. Post by ESP_igrr » Mon Nov 07, 2016 11:36 am . How to improve interrupt latency with Arduino/C. se » Wed Jun 16, 2021 9:17 am. We are using two external interrupts on the esp32, one interrupt is attached to core 1 (this is a high level interrupt on GPIO_NUM_35) and the other one is a low level interrupt which is tied to core 0 on GPIO_NUM_27. BlueRetro being a universal adapter with auto-detect at run time it's not possible to compile two versions. Post by ESP_igrr » Mon Nov 07, 2016 11:36 am . That needs 2 µs latency to start the waiting task RTOS_2 in core 0. Skip to content. External Interrupt Latency. We need to take some action when the interrupt is triggered (here: read a digital input). Each interrupt has a fixed priority, most (but not all) interrupts are connected to the interrupt matrix. Each interrupt has a certain priority level, most (but not all) interrupts are connected to the interrupt mux. Espressif ESP32 Official Forum. Now, the ESP32 is flashed with the new firmware. We’ll use the timer compare match interrupts (COMPA & COMPB) at the same time. Delta_G January 28, 2016, 1:40am 4.